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55 Open 235 Closed
55 Open 235 Closed
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Issues list

Initial values for clicintctl and clicintattr registers are not defined in the spec.
#461 opened Mar 17, 2025 by mark-honman
Possible conflict with behavior Machine mode for behavior of pending bits
#457 opened Mar 5, 2025 by christian-herber-nxp
1
Undo the removal of xie / xip
#456 opened Mar 5, 2025 by christian-herber-nxp
1
CSRs are defined as 32 bit also for RV64
#455 opened Mar 4, 2025 by christian-herber-nxp
align definition of clifcfg CSR with how its done in the priv manual
#453 opened Mar 4, 2025 by christian-herber-nxp
1
Value of xpil in case of a synchronous exception
#451 opened Feb 25, 2025 by christian-herber-nxp
@dansmathers
3
Value of clicintip when switching to edge-triggered mode should be defined
#450 opened Feb 24, 2025 by Timmmm
1
6
Unclarity related to possible interaction between mnxti CSR and Smdbltrp
#447 opened Feb 11, 2025 by Silabs-ArjanB
mtvec is not backwards compatible due to alignment
#446 opened Feb 4, 2025 by Timmmm
2
Note on relative priority of platform interrupts should cite sources
#445 opened Feb 4, 2025 by mark-honman
2
The contents of 7.2. should be moved to chapter 6.
#444 opened Jan 21, 2025 by hirooih
clicinttrig register interrupt_number should be 12 bits wide
#443 opened Jan 8, 2025 by mark-honman
create a new PR for https://github.com/riscv/riscv-fast-interrupt/pull/395 v1.0 resolve for 1.0
#441 opened Jan 6, 2025 by jb-brelot-nxp
@dansmathers
1
update PR #394 v1.0 resolve for 1.0
#440 opened Jan 6, 2025 by jb-brelot-nxp
@dansmathers
Possibility of maxid field in smclicconfig registers? v1.0 resolve for 1.0
#439 opened Jan 6, 2025 by mark-honman
@dansmathers
Conflicting statements about xnxti write side effects nxti v1.0 resolve for 1.0
#434 opened Nov 29, 2024 by Timmmm
@jb-brelot-nxp
MNXTI CSR clarifications? nxti
#433 opened Nov 14, 2024 by mark-honman
1
Clarify which CLIC CSRs are accessible in non-CLIC mode
#432 opened Nov 13, 2024 by mark-honman
Improve description of software examples v1.0 resolve for 1.0
#430 opened Nov 5, 2024 by mark-honman
1
Clarification of roles of MTVEC and MTVT nxti
#429 opened Nov 5, 2024 by mark-honman
1
Debug entry during hardware vectoring.
#428 opened Oct 14, 2024 by MarkHillCodasip
1
Spec doesn't say to clear the second lowest bit of trap handler addresses v1.0 resolve for 1.0
#427 opened Oct 14, 2024 by Timmmm
@jb-brelot-nxp
In Appendix, we should not have CLIC interrupt ID recommendation chapter. v1.0 resolve for 1.0
#426 opened Oct 7, 2024 by jb-brelot-nxp
@james-ball-qualcomm
1
clicintattr.mode should not be writable from S-mode v1.0 resolve for 1.0
#424 opened Oct 4, 2024 by christian-herber-nxp
@jb-brelot-nxp
1
Scratch Swap CSR (sscratchcswl) CSR section missing in ssclic chapter v1.0 resolve for 1.0
#422 opened Sep 30, 2024 by james-ball-qualcomm
@jb-brelot-nxp
ProTip! no:milestone will show everything without a milestone.