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Issues list

xcause.inhv conflicts with enabling CLIC per mode post-v1.0 To be handled after v1.0
#348 opened Aug 18, 2023 by JamesKenneyImperas
2
Allow xnxti to trigger on equal level as saved interrupt context. post-v1.0 To be handled after v1.0
#101 opened Sep 14, 2020 by David-Horner
1
This is the final version of preemptible interrupt handler of section 7.2 (no issue as such) post-v1.0 To be handled after v1.0
#102 opened Sep 14, 2020 by David-Horner
6
enhance support co-routines and thus allow level change already saved registers. post-v1.0 To be handled after v1.0
#106 opened Oct 5, 2020 by David-Horner
2
Heritage of features v1.0 resolve for 1.0
#107 opened Nov 10, 2020 by David-Horner
usefulness of PUSHINT/POPINT post-v1.0 To be handled after v1.0
#108 opened Dec 3, 2020 by Kevin-Andes
13
SAIL implementation of CLIC post-v1.0 To be handled after v1.0
#185 opened Dec 21, 2021 by dansmathers
5
CLIC Architecture tests post-v1.0 To be handled after v1.0
#186 opened Dec 21, 2021 by dansmathers
11
QEMU updates post-v1.0 To be handled after v1.0
#187 opened Dec 21, 2021 by dansmathers
1
Allow mix of CLIC/CLINT at different privilege modes post-v1.0 To be handled after v1.0
#192 opened Jan 18, 2022 by kasanovic
is spike support required? post-v1.0 To be handled after v1.0
#242 opened May 24, 2022 by dansmathers
4
Hypervisor mode should be discussed. post-v1.0 To be handled after v1.0
#248 opened Jun 21, 2022 by kasanovic
2
Hypervisor compatibility post-v1.0 To be handled after v1.0
#92 opened Jul 30, 2020 by JamesKenneyImperas
3
Add optional support for hardware register save e.g. shadow register sets? post-v1.0 To be handled after v1.0
#329 opened Apr 23, 2023 by brucehoult
3
How should non-normative text be specified in CLIC spec v1.0 resolve for 1.0
#376 opened Mar 5, 2024 by christian-herber-nxp
5
Require immediate evaluation of clicintie and clicintip v1.0 resolve for 1.0
#378 opened Mar 5, 2024 by Silabs-ArjanB
@james-ball-qualcomm
17
Missing a catchy terminology for the selection priority post-v1.0 To be handled after v1.0
#396 opened May 16, 2024 by christian-herber-nxp
@jb-brelot-nxp
6
Questions on Release 0.9 v1.0 resolve for 1.0
#398 opened Jul 15, 2024 by hirooih
@jb-brelot-nxp
1
an exception trap on the trap handler function address fetch cannot return to the instruction interrupted (smclicshv) v1.0 resolve for 1.0
#399 opened Jul 15, 2024 by hirooih
@james-ball-qualcomm
Make shv a per level property post-v1.0 To be handled after v1.0
#400 opened Aug 15, 2024 by christian-herber-nxp
@jb-brelot-nxp
1
Clarify behaviour of xnxti register version in smclicshv v1.0 resolve for 1.0
#402 opened Aug 27, 2024 by jakubahh
@jb-brelot-nxp
1
xscratchcswl privilege behaviour not fully specified v1.0 resolve for 1.0
#406 opened Sep 11, 2024 by Timmmm
@james-ball-qualcomm
2
The text definition of xscratchcswl is incomplete v1.0 resolve for 1.0
#407 opened Sep 11, 2024 by Timmmm
@james-ball-qualcomm
1
Explicitly list dependence on Smcsrind/Sscsrind v1.0 resolve for 1.0
#412 opened Sep 12, 2024 by christian-herber-nxp
@james-ball-qualcomm
Initial values for clicintctl and clicintattr registers are not defined in the spec.
#461 opened Mar 17, 2025 by mark-honman
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