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    60 repositories

    • riscv-isa-manual

      Public
      RISC-V Instruction Set Manual
      TeX
      •
      Creative Commons Attribution 4.0 International
      •686•4k•219•19•Updated Mar 19, 2025Mar 19, 2025

    • riscv-opcodes

      Public
      RISC-V Opcodes
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •317•733•30•28•Updated Mar 19, 2025Mar 19, 2025

    • riscv-cheri

      Public
      This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
      memory-safetycapabilitiescompartmentalization
      Python
      •
      Creative Commons Attribution 4.0 International
      •35•63•42•1•Updated Mar 19, 2025Mar 19, 2025

    • riscv-aia

      Public
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •19•86•30•1•Updated Mar 19, 2025Mar 19, 2025

    • riscv-spmp

      Public
      The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by an hart, address matching, encoding of permissions, exceptions for access violation, and support for virtualization.
      TeX
      •
      Creative Commons Attribution 4.0 International
      •9•13•1•0•Updated Mar 18, 2025Mar 18, 2025

    • sail-riscv

      Public
      Sail RISC-V model
      C
      •
      Other
      •192•511•103•84•Updated Mar 18, 2025Mar 18, 2025

    • riscv-performance-events

      Public
      RISC-V Performance Events Specification
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •5•4•0•1•Updated Mar 17, 2025Mar 17, 2025

    • riscv-docs-base-container-image

      Public
      A base container image populated with the dependencies to build the RISC-V Documentation.
      Apache License 2.0
      •8•10•0•4•Updated Mar 17, 2025Mar 17, 2025

    • meta-riscv

      Public
      OpenEmbedded/Yocto layer for RISC-V Architecture
      riscvyocto-layeryoctoopenembeddedyocto-metaopenembedded-layerrisc-v
      BitBake
      •
      Other
      •147•380•17•1•Updated Mar 16, 2025Mar 16, 2025

    • riscv-dot-product

      Public
      Dot-Product Extension
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •4•4•3•3•Updated Mar 14, 2025Mar 14, 2025

    • riscv-memory-tagging

      Public
      Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •6•13•6•3•Updated Mar 11, 2025Mar 11, 2025

    • docs-dev-guide

      Public
      Documentation developer guide
      TeX
      •
      Creative Commons Attribution 4.0 International
      •35•99•4•3•Updated Mar 11, 2025Mar 11, 2025

    • composable-custom-extensions

      Public
      This task group will propose ISA extension(s) and non-ISA hardware and software interop interfaces to enable routine reuse and composition of a subcategory of custom extensions called composable extensions.
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •1•3•1•1•Updated Mar 11, 2025Mar 11, 2025

    • riscv-fast-interrupt

      Public
      Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •50•260•55•7•Updated Mar 7, 2025Mar 7, 2025

    • wordguard

      Public
      WorldGuard (WG) provides isolation in a hardware platform by constraining access to system physical addresses.
      TeX
      •
      Creative Commons Attribution 4.0 International
      •686•0•0•0•Updated Mar 7, 2025Mar 7, 2025

    • Svrsw60t59b

      Public
      PTE Reserved-for-Software Bits 60-59
      TeX
      •
      Creative Commons Attribution 4.0 International
      •686•0•0•0•Updated Mar 7, 2025Mar 7, 2025

    • riscv-smmtt

      Public
      This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant security use cases e.g. confidential-computing, trusted platform services, fault isolation and so on.
      access-controltrusted-computingtrusted-execution-environmentconfidential-computingsmmttsupervisor-domainsap-tee
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •18•46•3•0•Updated Feb 27, 2025Feb 27, 2025

    • riscv-debug-spec

      Public
      Working Draft of the RISC-V Debug Specification Standard
      Python
      •
      Other
      •95•478•58•6•Updated Feb 25, 2025Feb 25, 2025

    • riscv-sdtrigepm

      Public
      Sdtrig Effective Privilege Mode (Sdtrigepm) Fast-track ISA Extension
      TeX
      •
      Creative Commons Attribution 4.0 International
      •686•0•0•0•Updated Feb 24, 2025Feb 24, 2025

    • riscv-zilsd

      Public
      Zilsd (Load/Store Pair for RV32) Fast-Track Extension
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •5•9•0•1•Updated Feb 21, 2025Feb 21, 2025

    • docs-spec-template

      Public template
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •22•24•3•2•Updated Feb 21, 2025Feb 21, 2025

    • riscv-cfi

      Public
      This specification is integrated into the Priv. and Unpriv. specifications. This repo is no longer maintained. Please refer to the Priv. and Unpriv. specifications at https://github.com/riscv/riscv-isa-manual
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •22•86•0•0•Updated Feb 20, 2025Feb 20, 2025

    • riscv-performance-event-sampling

      Public
      Define 2 new extensions to, along with Zihpm and Sscofpmf, enable event and instruction sampling with precise attribution.
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •1•0•0•1•Updated Feb 20, 2025Feb 20, 2025

    • sig-functional-safety-whitepaper

      Public
      GitHub repository for the Functional Safety SIG Whitepaper Development
      TeX
      •
      Creative Commons Attribution 4.0 International
      •2•2•0•2•Updated Feb 20, 2025Feb 20, 2025

    • riscv-svvptc

      Public
      Obviating Memory-Management Instructions after Marking PTEs Valid (Svvptc)
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •4•2•0•0•Updated Feb 19, 2025Feb 19, 2025

    • riscv-b

      Public
      "B" extension - that represents the collection of the Zba, Zbb, and Zbs extensions
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •4•6•0•0•Updated Feb 19, 2025Feb 19, 2025

    • riscv-ssdtso

      Public
      The Ssdtso is a fast-track extension adding a 'dynamic-RVTSO' mode of operation and on-demand per-hart switching between the memory models.
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •2•1•0•1•Updated Feb 19, 2025Feb 19, 2025

    • riscv-zalasr

      Public
      The ISA specification for the Zalasr extension.
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •2•3•3•1•Updated Feb 19, 2025Feb 19, 2025

    • riscv-glossary

      Public
      Makefile
      •6•7•12•0•Updated Feb 19, 2025Feb 19, 2025

    • riscv-zabha

      Public
      The Zabha extension provides support for byte and halfword atomic memory operations.
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •8•8•0•1•Updated Feb 19, 2025Feb 19, 2025