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Issues: unihd-cag/odfi-rfg

26 Open 44 Closed
26 Open 44 Closed
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Issues list

add scala menu generator feature
#92 opened Aug 18, 2017 by swittka v1.2.0
@swittka
hardware ro clear generation fails bug
#90 opened May 5, 2017 by TM90
@TM90
Support of new rf macros in e-generator enhancement
#89 opened Apr 3, 2017 by swittka v1.2.0
@swittka
Add RTF generator
#88 opened Mar 31, 2017 by TM90
@TM90
Counter with clear signal enhancement
#87 opened Nov 3, 2016 by jurischmidt
synthesisable System Verilog SW Interface enhancement
#86 opened Sep 5, 2016 by TM90
@TM90
More compact register attribute definitions feature
#85 opened Aug 29, 2016 by markuslsra v1.2.0
@TM90
1
Register Maximal width is wrongly supported
#68 opened Oct 28, 2015 by richnou
Support for FIFO register feature
#66 opened Oct 2, 2015 by richnou
Defines full names bug
#61 opened Sep 2, 2015 by TM90
@TM90
ones and zero statement for fields enhancement
#59 opened Sep 2, 2015 by TM90
@TM90
Loop variable rfs_to_rfg bug
#58 opened Sep 2, 2015 by TM90
@TM90
e generator for hw interface feature
#57 opened Sep 1, 2015 by swittka v1.2.0
@swittka
System Verilog Generator feature
#41 opened Apr 13, 2015 by TM90
@swittka
refactor VerilogGenerator Helperfunctions enhancement
#37 opened Mar 21, 2015 by TM90 v1.2.0
@TM90
hardware_rreinit feature
#35 opened Feb 27, 2015 by TM90 v1.2.0
Enhanced counters feature
#34 opened Feb 27, 2015 by TM90 v1.2.0
VerilogGenerator read data, write data different width enhancement
#30 opened Feb 19, 2015 by TM90 v1.2.0
@TM90
Remove invalid address (and perhaps the address itself?) for single reg RF enhancement
#27 opened Feb 11, 2015 by jurischmidt v1.2.0
@TM90
Multi-bit Counter enhancement
#16 opened Dec 16, 2014 by jurischmidt v1.2.0
@TM90
Generator C/C++ Defines feature
#15 opened Dec 9, 2014 by TM90 v1.2.0
1
Generate repeat block internally as array feature
#12 opened Nov 7, 2014 by TM90 v1.2.0
fields for ramBlocks feature
#10 opened Nov 7, 2014 by TM90 v1.2.0
parameter for external registerfiles feature
#8 opened Nov 7, 2014 by TM90 v1.2.0
@TM90
script to read in verilog defines feature
#7 opened Nov 7, 2014 by TM90 v1.2.0
@TM90
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