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Add GCMODE instruction #350

Merged
merged 3 commits into from
Aug 29, 2024
Merged

Add GCMODE instruction #350

merged 3 commits into from
Aug 29, 2024

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andresag01
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@andresag01 andresag01 commented Aug 28, 2024

Add GCMODE instruction that decodes the mode from an arbitrary capability in an x register and writes the value to another x register.

GCMODE allows inspecting a capability's CHERI execution mode without the need for software to "manually" decode the capability's metadata using gchi.

Fixes #302.

@andresag01 andresag01 merged commit d63f4b5 into riscv:main Aug 29, 2024
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tariqkurd-repo pushed a commit to tariqkurd-repo/riscv-cheri that referenced this pull request Oct 9, 2024
Add GCMODE instruction that decodes the mode from an arbitrary
capability in an *x* register and writes the value to another *x*
register.

GCMODE allows inspecting a capability's CHERI execution mode without the
need for software to "manually" decode the capability's metadata using
`gchi`.

Fixes riscv#302.
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No GCMODE
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