Support for RISC-V

[dipinhora]

Support for riscv. All tests pass for the 64 bit target.

---

Instructions for testing (validated on ubuntu 20.04):

# install cross compiling toolchain
sudo apt-get install -y gdb-multiarch qemu-user gcc-10-riscv64-linux-gnu g++-10-riscv64-linux-gnu

# soft link riscv libs to the right path for qemu based execution to work
ln -s /usr/riscv64-linux-gnu/lib/* /lib

# clean old build artifacts/state (including llvm)
make distclean

# compile libs/llvm with support for X86/RISCV
make libs llvm_archs='X86;RISCV' build_flags='-j8'

# configure for X86/RISCV ponyc
make config=debug configure llvm_archs='X86;RISCV' build_flags='-j8'

# build for X86/RISCV ponyc
make config=debug build llvm_archs='X86;RISCV' build_flags='-j8'

# run tests for normal X86 ponyc
make config=debug test llvm_archs='X86;RISCV' build_flags='-j8'

# cross compile libponyrt-pic for RISCV
make config=debug cross-libponyrt CC=riscv64-linux-gnu-gcc-10 CXX=riscv64-linux-gnu-g++-10 arch=rv64gc cross_cflags="-march=rv64gc -mtune=rocket" cross_lflags="-march=riscv64"

# cross compile stdlib and run it in qemu
make config=debug test-cross-ci PONYPATH=../rv64gc/debug cross_triple=riscv64-unknown-linux-gnu cross_arch=rv64gc cross_cpu=generic-rv64 cross_linker=riscv64-linux-gnu-gcc-10 cross_ponyc_args='--abi=lp64d --features=+m,+a,+f,+d,+c --link-ldcmd=bfd' cross_runner="qemu-riscv64 -L /usr/riscv64-linux-gnu/lib/" verbose=1

[SeanTAllen]

Does the exception problem only happen in debug or release mode or does it happen with both?

[dipinhora]

@SeanTAllen that problem has magically gone away on it's own (you saw the old description before i edited it).

[SeanTAllen]

That's... concerning. So if run enough we might see the problem again?

[dipinhora]

i believe it got resolved due to the 2.5 years of changes to pony

[SeanTAllen]

@dipinhora can you add CI for this as part of the PR?

[ponylang-main]

Hi @dipinhora,

The changelog - added label was added to this pull request; all PRs with a changelog label need to have release notes included as part of the PR. If you haven't added release notes already, please do.

Release notes are added by creating a uniquely named file in the .release-notes directory. We suggest you call the file 3435.md to match the number of this pull request.

The basic format of the release notes (using markdown) should be:

## Title

End user description of changes, why it's important,
problems it solves etc.

If a breaking change, make sure to include 1 or more
examples what code would look like prior to this change
and how to update it to work after this change.

Thanks.

[dipinhora]

@dipinhora can you add CI for this as part of the PR?

Added riscv64 CI stuff.. will probably fail cause the container image doesn't exist...

[SeanTAllen]

Oh yeah. Huh. How can we get a container built.

[dipinhora]

@SeanTAllen i tried to build and push the image to the ponylang docker repo but i don't have permissions (which makes perfect sense):

$ docker push "ponylang/ponyc-ci-cross-riscv64:20220715"
The push refers to repository [docker.io/ponylang/ponyc-ci-cross-riscv64]
9fc339d915bc: Preparing
dff34515e55b: Preparing
aecbe6390165: Preparing
3fdc0d4966e3: Preparing
5e093e475d77: Preparing
259c12df0273: Waiting
9c75c22ceed8: Waiting
denied: requested access to the resource is denied

i'd appreciate it if you can build/push the new image. Let me know if i need to update the image tag in this PR if it's different from ponylang/ponyc-ci-cross-riscv64:20220715.

[SeanTAllen]

@dipinhora i pushed Successfully tagged ponylang/ponyc-ci-cross-riscv64:20220716

[SeanTAllen]

@dipinhora one final thing before this gets merged, can you update README.md to add RiscV as a supported CPU type? 64-bit only as that is what we do CI for. Feel free to change the formatting on the supported CPU section as it is odd and hard to read. A simple listing might be better. I don't know. Really, that should be CPU + OS support listed and not separated out as we don't officially support Windows Arm for example.