Skip to content

Apache 2.0 licensed copy of the Xilinx Unisim library.

License

Notifications You must be signed in to change notification settings

SymbiFlow/XilinxUnisimLibrary

This branch is up to date with Xilinx/XilinxUnisimLibrary:master.

Folders and files

NameName
Last commit message
Last commit date

Latest commit

1c8e05f · Jul 22, 2020

History

2 Commits
Jul 22, 2020
Jun 25, 2020
Jun 25, 2020

Repository files navigation

Xilinx Unisim Library

The Xilinx Unisim Library Verilog available as open source under Apache 2.0.

These files coincide with the 2020.1 release of Vivado.

Releases

No releases published

Packages

No packages published

Languages

  • Verilog 97.8%
  • SystemVerilog 2.2%