Timing fixes #6
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Timing fixes #6
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This pull request contains a lot of embarrassing timing fixes. Things like ... signals bypassing the asynchronous FIFO, asynchronous FIFOs running on the wrong clock domain, signals in clock domain X clocked in domain Y, only to be returned to domain X, etc. These fixes are in the data path, so you may struggle to get things working without these fixes.
Also ... I swapped which byte was checked for the correct FIS, used to determine when to update regs and when to send data to the DMA. This could break current sims, and so needs to be double checked.