AUDIY_Verilog_IP

Verilog IP that AUDIY originally designed.
Code reviews are welcome!

Modules List

• DIFFERENTIATOR
  Differentiator.
• I2S_PCM_BCLK
  I2S to stereo PCM converter (synchronous w/ Bit clock).
• INTEGRATOR
  Forward & Back eular method integrator.
• Memory
  Memory code examples.
  Note: It is recommended to use vendor original ROM/RAM IP.
• ARESETN_SYNC
  Asynchronous Reset (Active LOW) Synchronizer.
• __Legacy__
  Modules no longer maintained.

Legacy Modules List

• I2S_MCLK
  I2S to stereo PCM converter (synchronous w/ Master clock).
  I2S must be synchronized w/ MCLK by synchronizer. So it is NOT recommended.

License under CERN-OHL-P v2

Copyright AUDIY 2023 - 2025.

This source describes Open Hardware and is licensed under the CERN-OHL-P v2.

You may redistribute and modify this source and make products using it under the terms of the CERN-OHL-P v2 (https:/cern.ch/cern-ohl).

This source is distributed WITHOUT ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY AND FITNESS FOR A PARTICULAR PURPOSE.
Please see the CERN-OHL-P v2 for applicable conditions.