An RTL generator for a last-level shared inclusive TileLink cache controller

RISC-V CPU Core

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Common RTL blocks used in SiFive's projects

Wrapper shells enabling designs generated by rocket-chip to map onto certain FPGA boards

AgonLight OSHW Retro Z80 computer - updated version with few updates

Custom 16-bit homebrew CPU, emulator, renderer, circuit, and language

RISC-V Torture Test

Lab exercises for Chisel in the digital electronics 2 course at DTU

A stand-alone, BASIC-programmable microcontroller and microcomputer in one! The fastest, cheapest, most hackable 8-bit computer ever.

Library to compile Chisel circuits using LLVM/MLIR (CIRCT)

Rocket Chip Generator

RISC-V emulator writen in Scala

Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.

A RISC-V Core (RV32I) written in Chisel HDL

A RISC-V assembler library for Scala/Chisel HDL projects

mos6502 emulator in Scala

chisel tutorial exercises and answers

A Chisel RTL generator for network-on-chip interconnects

Chisel/Firrtl execution engine

Flexible Intermediate Representation for RTL

FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL

Simple RISC-V 3-stage Pipeline in Chisel

Provides various testers for chisel users

Chisel examples and code snippets

Scala based HDL

A template project for beginning new Chisel work

Digital Design with Chisel