AARCH64 CPUs with GICv2 using IRQs and FIQs to provide Non-secure and Secure interrupts not working

[mfrank41]

Using IRQs and FIQs to provide Non-secure and Secure interrupts as described by ARM here is currently not supported by renode.

If the FIQs are routed to EL3 while keep the IRQs in EL1 leads to the following error:

14:17:38.6548 [ERROR] cpu: CPU abort [PC=0x400075B8]: Unexpected register state in process_interrupt!.

I was able to fix it by the following dirty hack in the tlib:

diff --git a/arch/arm64/helper.c b/arch/arm64/helper.c
index 52f4d46..1da29ce 100644
--- a/arch/arm64/helper.c
+++ b/arch/arm64/helper.c
@@ -972,7 +972,7 @@ int process_interrupt_v8a_aarch32(int interrupt_request, CPUState *env, uint64_t
 }
 
 #define IRQ_IGNORED UINT32_MAX
-uint32_t establish_interrupts_target_el(uint32_t current_el, uint64_t scr_el3, uint64_t hcr_el2)
+uint32_t establish_interrupts_target_el(uint32_t current_el, uint64_t scr_el3, uint64_t hcr_el2, int interrupt_request)
 {
     tlib_assert(current_el <= 3);
 
@@ -1222,6 +1222,11 @@ uint32_t establish_interrupts_target_el(uint32_t current_el, uint64_t scr_el3, u
             tlib_abortf("Invalid SCR_EL3 (0x%" PRIx64 ") and HCR_EL2 (0x%" PRIx64 ") for an EL1 interrupt", scr_el3, hcr_el2);
             break;
         }
+    } else if (check_scr_el3(scr_el3, 1, -1, -1, 0, 1, -1)) {
+        if(interrupt_request & CPU_INTERRUPT_FIQ)
+            return 3;
+        else
+            return 1;
     } else {
         tlib_abortf("Unexpected register state in process_interrupt!");
     }
@@ -1235,7 +1240,7 @@ int process_interrupt_v8a_aarch64(int interrupt_request, CPUState *env, uint64_t
     uint32_t current_el = arm_current_el(env);
     uint32_t target_el = 1;
 
-    target_el = establish_interrupts_target_el(current_el, scr_el3, hcr_el2);
+    target_el = establish_interrupts_target_el(current_el, scr_el3, hcr_el2, interrupt_request);
 
     if (target_el == IRQ_IGNORED) {
         return 0;