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/*
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- * Copyright (c) 2023 , Advanced Micro Devices, Inc.
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+ * Copyright (c) 2024 , Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Author: Chris Lavin, Advanced Micro Devices, Inc.
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/**
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- * Generated on: Fri Oct 20 23:25:44 2023
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+ * Generated on: Wed May 01 19:57:08 MDT 2024
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* by: com.xilinx.rapidwright.release.SiteAndTileTypeUpdater
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*
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* Enumeration of TileTypeEnum type for all valid devices within Vivado.
@@ -626,6 +626,8 @@ public enum TileTypeEnum {
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GTH_DA7_TERM_L_RBRK ,
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GTH_DA7_TERM_L_TERM_P ,
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GTH_DA7_TERM_L_TERM_T ,
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+ GTH_DR1_TERM_L_FT ,
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+ GTH_DR1_TERM_L_TERM_B_FT ,
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GTH_INT_INTERFACE ,
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GTH_INT_INTERFACE_L ,
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GTH_QUAD_HPIO_RBRK_FT ,
@@ -636,6 +638,7 @@ public enum TileTypeEnum {
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GTH_QUAD_LEFT_FT ,
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GTH_QUAD_LEFT_RBRK ,
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GTH_QUAD_LEFT_RBRK_FT ,
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+ GTH_QUAD_LEFT_TERM_B_FT ,
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GTH_QUAD_LEFT_TERM_T ,
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GTH_QUAD_LEFT_TERM_T_FT ,
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GTH_QUAD_RIGHT ,
@@ -778,9 +781,14 @@ public enum TileTypeEnum {
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HDIO_HDIO_FILL_PCIE4_RBRK_FT ,
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HDIO_HDIO_FILL_RBRK_FT ,
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HDIO_HDIO_FILL_TERM_T_FT ,
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+ HDIO_HDIO_LEFT_TERM_T_FT ,
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HDIO_HDIO_RIGHT_TERM_P_FT ,
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HDIO_HDIO_RIGHT_TERM_RBRK_FT ,
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HDIO_ILKN_RBRK_FT ,
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+ HDIO_OUTER_TERM_R_FT ,
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+ HDIO_OUTER_TERM_R_RBRK_FT ,
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+ HDIO_OUTER_TERM_R_TERM_B_FT ,
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+ HDIO_OUTER_TERM_R_TERM_T_FT ,
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HDIO_PCIE4_RBRK_FT ,
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HDIO_RIGHT_CFG_TERM_T ,
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HDIO_RIGHT_RBRK ,
@@ -806,7 +814,15 @@ public enum TileTypeEnum {
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HPIO_CFG_TERM_L_TOP_FT ,
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HPIO_CFG_TOP_TERM_R ,
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HPIO_CFG_TOP_TERM_R_GTH ,
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+ HPIO_GTH_AUX_IO_TERM_L_BOT_FT ,
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+ HPIO_GTH_AUX_IO_TERM_L_TOP_FT ,
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+ HPIO_GTH_CFG_TERM_L_BOT_FT ,
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+ HPIO_GTH_CFG_TERM_L_TOP_FT ,
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+ HPIO_GTH_QUAD_LEFT_RBRK_FT ,
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HPIO_GTH_QUAD_RIGHT_RBRK_FT ,
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+ HPIO_GTH_TERM_L_M_RBRK_FT ,
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+ HPIO_GTH_TERM_L_RBRK_FT ,
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+ HPIO_GTH_TERM_L_TERM_T_FT ,
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HPIO_HPIO_LEFT_TERM_B_L_FT ,
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HPIO_HPIO_LEFT_TERM_P_FT ,
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HPIO_HPIO_LEFT_TERM_T_L_FT ,
@@ -991,6 +1007,7 @@ public enum TileTypeEnum {
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INT_INTF_LEFT_IBRK_IO_TERM_H_FT ,
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INT_INTF_LEFT_IBRK_PCIE4_TERM_H_FT ,
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INT_INTF_LEFT_IBRK_PCIE4_TERM_P_FT ,
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+ INT_INTF_LEFT_TERM_GT_IO_RBRK_FT ,
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INT_INTF_LEFT_TERM_GT_TERM_H_FT ,
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INT_INTF_LEFT_TERM_GT_TERM_P ,
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INT_INTF_LEFT_TERM_H_FT ,
@@ -1028,6 +1045,7 @@ public enum TileTypeEnum {
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INT_INTF_RIGHT_IO_TERM_B ,
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INT_INTF_RIGHT_TERM_GT_IO_RBRK ,
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INT_INTF_RIGHT_TERM_GT_TERM_H_FT ,
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+ INT_INTF_RIGHT_TERM_HDIO_FT ,
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INT_INTF_RIGHT_TERM_H_FT ,
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INT_INTF_RIGHT_TERM_IO ,
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INT_INTF_RIGHT_TERM_IO_TERM_T ,
@@ -1425,6 +1443,9 @@ public enum TileTypeEnum {
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RCLK_RCLK_DSP_INTF_DC12_L_FT ,
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RCLK_RCLK_DSP_INTF_DC12_R_FT ,
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RCLK_RCLK_GAP50_MINICBRK_FT ,
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+ RCLK_RCLK_HDIO_LAST_R_FT ,
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+ RCLK_RCLK_HDIO_R_FT ,
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+ RCLK_RCLK_HPIO_GTH_TERM_L_FT ,
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RCLK_RCLK_HPIO_TERM_L_DA6_FT ,
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RCLK_RCLK_HPIO_TERM_L_FT ,
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RCLK_RCLK_IBRK_FSR2FE_FT ,
@@ -1438,9 +1459,11 @@ public enum TileTypeEnum {
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RCLK_RCLK_INTF_LEFT_TERM_DA6_FT ,
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RCLK_RCLK_INTF_LEFT_TERM_DA8_FT ,
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RCLK_RCLK_INTF_LEFT_TERM_DC12_FT ,
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+ RCLK_RCLK_INTF_LEFT_TERM_GT_IO_FT ,
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RCLK_RCLK_INTF_LEFT_TERM_IO_FT ,
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RCLK_RCLK_INTF_LEFT_TERM_MX8_FT ,
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RCLK_RCLK_INTF_PCIE3_LEFT_L_FT ,
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+ RCLK_RCLK_INTF_RIGHT_IBRK_PCIE4_R_FT ,
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RCLK_RCLK_INTF_XIPHY_LEFT_L_FT ,
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RCLK_RCLK_K3_TERM_L_FT ,
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RCLK_RCLK_LAGUNA_L_FT ,
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