How to extract RS1/RS2 value for debugging?

[esyvjlomh]

Hello,

I tried to customize the WhiteboxerPlugin, attempting to extract the rs1/rs2 data to the toplevel output of the CPU core so that I could debug more precisely. The addrs of rs1/rs2 are simple to get via the uop, but I do not know how to extract the data in the register.

I tried to modify Plugin's code like (WhiteboxerPlugin.scala):

val executes = for (eu <- host.list[ExecuteLaneService]) yield new Area {
      val c = eu.ctrl(eu.executeAt)
      val fire = wrap(c.down.transactionSpawn && c.down(Global.COMMIT))
      val hartId = wrap(c(Global.HART_ID))
      val microOpId = wrap(c(Decode.UOP_ID))

// Added part.
      val n = Node()
      var rs1 = Bits(32 bits)
      var rs2 = Bits(32 bits)
      rs1 = n(eu.apply(IntRegFile, RS1))
      val rs1_out = wrap(rs1)
      rs2 = n(eu.apply(IntRegFile, RS2))
      val rs2_out = wrap(rs2)
    }

I checked Service.scala,

// API which allows to get the pipeline Payload to access the RS1/RS2 hardware values
  def getStageable(r: RfResource): Payload[Bits]
  def apply(rf: RegfileSpec, access: RfAccess) = getStageable(rf -> access)
  def apply(r: RfResource) = getStageable(r)

and use Node() which seems like a useful tool, but I cannot generate verilog code. The error looks like:

[error] Exception in thread "main" spinal.core.SpinalExit:
[error]  Error detected in phase PhaseCheck_noLatchNoOverride
[error] ********************************************************************************
[error] ********************************************************************************
[error] NO DRIVER ON (toplevel/WhiteboxerPlugin_logic_executes_0_n_integer_RS2 :  Bits[32 bits]), defined at
[error]     vexiiriscv.execute.ExecuteLanePlugin.$anonfun$getStageable$2(ExecuteLanePlugin.scala:73)
[error]     spinal.lib.misc.pipeline.NodeApi.$anonfun$apply$2(Node.scala:101)
[error]     spinal.lib.misc.pipeline.NodeApi.apply(Node.scala:101)
[error]     spinal.lib.misc.pipeline.NodeApi.apply$(Node.scala:97)
[error]     spinal.lib.misc.pipeline.Node.apply(Node.scala:175)
[error]     spinal.lib.misc.pipeline.NodeApi.apply(Node.scala:115)
[error]     spinal.lib.misc.pipeline.NodeApi.apply$(Node.scala:115)
[error]     spinal.lib.misc.pipeline.Node.apply(Node.scala:175)
[error]     vexiiriscv.test.WhiteboxerPlugin$Logic$$anon$5.<init>(WhiteboxerPlugin.scala:146)
[error]     vexiiriscv.test.WhiteboxerPlugin$Logic.$anonfun$executes$1(WhiteboxerPlugin.scala:130)
[error]     vexiiriscv.test.WhiteboxerPlugin$Logic.<init>(WhiteboxerPlugin.scala:130)
[error]     vexiiriscv.test.WhiteboxerPlugin.$anonfun$logic$1(WhiteboxerPlugin.scala:39)
[error]     spinal.lib.misc.plugin.FiberPlugin$$anon$1.$anonfun$setup$4(Fiber.scala:71)
[error]     spinal.lib.misc.plugin.PluginHost.rework(Host.scala:29)
[error]     spinal.lib.misc.plugin.FiberPlugin$$anon$1.$anonfun$setup$2(Fiber.scala:69)
[error]     spinal.lib.misc.plugin.FiberPlugin$$anon$1.$anonfun$setup$1(Fiber.scala:66)
[error] ********************************************************************************
[error] ********************************************************************************

I simulate the CPU core and detect the signals with verilator and gtkwave, but I cannot find a signal that matches RS1/RS2 data precisely. How should I modify the code to extract the precise register data?

Appreciate it if some guidance can be given!