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Issues list

Unused registers
#78 opened Jun 16, 2019 by dnltz
1
Briey DE0 Nano SoC, not enough I/O pin locations
#22 opened May 29, 2018 by Lestandin
3
Can VexRISCV based SoC be made to fit on an iCE40 1k?
#28 opened Jun 25, 2018 by mithro
8
VexRiscv configuration doesn't trap on misaligned branch
#37 opened Aug 7, 2018 by tomverbeure
1
File name <> Module name inconsistent
#38 opened Aug 8, 2018 by tomverbeure
2
RV32E support
#42 opened Nov 8, 2018 by xobs
4
Congratulations for winning 1st place of SoftCPU contest!
#45 opened Dec 6, 2018 by drom
1
Create wiki
#47 opened Dec 18, 2018 by cutephoton
11
Correct spelling?
#56 opened Feb 21, 2019 by secworks
1
Mul/Div don't work if withWriteBackStage or withMemoryStage is false
#61 opened Mar 13, 2019 by xobs
1
Provide MMU / MemoryTranslatorPlugin example
#63 opened Mar 16, 2019 by xobs
5
Add a pipeline description to gcc
#68 opened Mar 27, 2019 by futaris
6
GDB not working with FPGA
#4 opened Oct 4, 2017 by albaEDA
23
Benchmark VexRISCV using embench
#77 opened Jun 12, 2019 by mithro
11
Add support for fast register saving
#81 opened Jul 26, 2019 by mithro
3
illegal instruction with Zephyr
#82 opened Aug 10, 2019 by FrankBuss
2
RiscV A "AMO" with DBusSimplePlugin
#83 opened Aug 12, 2019 by BlamKiwi
3
vexriscv.MuraxSim error in Windows 10 using the latest github clone
#84 opened Sep 9, 2019 by flylandcs
5
Tightly coupled memory
#91 opened Oct 9, 2019 by 9ary
6
Have you seen pqriscv-vexriscv?
#92 opened Oct 9, 2019 by mithro
1
RV32IMC with IBusCachedPlugin
#93 opened Oct 16, 2019 by MarekPikula
11
Vectored interrupt support
#96 opened Nov 7, 2019 by MarekPikula
9
Spec-compliant debug interface
#97 opened Nov 8, 2019 by MarekPikula
11
WFI: System can't be reset via DebugPlugin
#98 opened Nov 19, 2019 by xobs
16
Vexriscv dual-core smp architecture has a problem when debugging
#446 opened Mar 11, 2025 by TieTouXiaoGe
5
ProTip! Updated in the last three days: updated:>2025-03-27.